arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/aspeed/aspeed-g7-soc1.dtsi- Extension
.dtsi- Size
- 14128 bytes
- Lines
- 558
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/aspeed,ast2700-scu.hdt-bindings/reset/aspeed,ast2700-scu.hdt-bindings/interrupt-controller/aspeed-scu-ic.haspeed-g7-soc1-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AST27xx SoC Family Main Domain peripherals
*
* Copyright (C) 2026 ASPEED Technology Inc.
*/
#include <dt-bindings/clock/aspeed,ast2700-scu.h>
#include <dt-bindings/reset/aspeed,ast2700-scu.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
&soc1 {
fmc: spi@14000000 {
reg = <0x0 0x14000000 0x0 0xc4>, <0x1 0x00000000 0x0 0x80000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2700-fmc";
status = "disabled";
clocks = <&syscon1 SCU1_CLK_AHB>;
interrupts-extended = <&intc1 121>;
num-cs = <3>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
status = "disabled";
};
};
spi0: spi@14010000 {
reg = <0x0 0x14010000 0x0 0xc4>, <0x1 0x80000000 0x0 0x80000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2700-spi";
clocks = <&syscon1 SCU1_CLK_AHB>;
interrupts-extended = <&intc1 122>;
status = "disabled";
num-cs = <2>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
Annotation
- Immediate include surface: `dt-bindings/clock/aspeed,ast2700-scu.h`, `dt-bindings/reset/aspeed,ast2700-scu.h`, `dt-bindings/interrupt-controller/aspeed-scu-ic.h`, `aspeed-g7-soc1-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.