arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts- Extension
.dts- Size
- 4757 bytes
- Lines
- 185
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
bm1880.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Linaro Ltd.
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
/dts-v1/;
#include "bm1880.dtsi"
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "sophon-edge-schematics"
* version, 1.0210.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence. This is only for the informational
* lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
* are the only ones actually used for GPIO.
*/
/ {
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
model = "Sophon Edge";
aliases {
serial0 = &uart0;
serial1 = &uart2;
serial2 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
};
soc {
gpio0: gpio@50027000 {
porta: gpio-controller@0 {
gpio-line-names =
"GPIO-A", /* GPIO0, LSEC pin 23 */
"GPIO-C", /* GPIO1, LSEC pin 25 */
"[GPIO2_PHY0_RST]", /* GPIO2 */
"GPIO-E", /* GPIO3, LSEC pin 27 */
"[USB_DET]", /* GPIO4 */
"[EN_P5V]", /* GPIO5 */
"[VDDIO_MS1_SEL]", /* GPIO6 */
"GPIO-G", /* GPIO7, LSEC pin 29 */
"[BM_TUSB_RST_L]", /* GPIO8 */
"[EN_P5V_USBHUB]", /* GPIO9 */
"NC",
"LED_WIFI", /* GPIO11 */
"LED_BT", /* GPIO12 */
"[BM_BLM8221_EN_L]", /* GPIO13 */
"NC", /* GPIO14 */
Annotation
- Immediate include surface: `bm1880.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.