arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts- Extension
.dts- Size
- 2993 bytes
- Lines
- 120
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
blaize-blzp1600-som.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
*/
/dts-v1/;
#include "blaize-blzp1600-som.dtsi"
/ {
model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
status = "okay";
gpio_expander: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
"RSP_PIN_11", /* GPIO_1 */
"RSP_PIN_13", /* GPIO_2 */
"RSP_PIN_15", /* GPIO_3 */
"RSP_PIN_27", /* GPIO_4 */
"RSP_PIN_29", /* GPIO_5 */
"RSP_PIN_31", /* GPIO_6 */
"RSP_PIN_33", /* GPIO_7 */
"RSP_PIN_37", /* GPIO_8 */
"RSP_PIN_16", /* GPIO_9 */
"RSP_PIN_18", /* GPIO_10 */
"RSP_PIN_22", /* GPIO_11 */
"RSP_PIN_28", /* GPIO_12 */
"RSP_PIN_32", /* GPIO_13 */
"RSP_PIN_36", /* GPIO_14 */
"TP31"; /* GPIO_15 */
};
gpio_expander_m2: gpio@75 {
compatible = "ti,tca9539";
reg = <0x75>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
"M2_W_DIS2_N", /* GPIO_1 */
"M2_UART_WAKE_N", /* GPIO_2 */
"M2_COEX3", /* GPIO_3 */
"M2_COEX_RXD", /* GPIO_4 */
Annotation
- Immediate include surface: `blaize-blzp1600-som.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.