arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
Extension
.dtsi
Size
4788 bytes
Lines
218
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2024 Blaize, Inc. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	firmware {
		scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0x82002000>;
			#address-cells = <1>;
			#size-cells = <0>;

			shmem = <&scmi0_shm>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_rst: protocol@16 {
				reg = <0x16>;
				#reset-cells = <1>;
			};
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

Annotation

Implementation Notes