arch/arm64/boot/dts/broadcom/bcm2712.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/broadcom/bcm2712.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
Extension
.dtsi
Size
19964 bytes
Lines
708
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/bcm2835-pm.h>

/ {
	compatible = "brcm,bcm2712";

	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gicv2>;

	clocks {
		/* The oscillator is the root of the clock tree. */
		clk_osc: clk-osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "osc";
			clock-frequency = <54000000>;
		};

		clk_vpu: clk-vpu {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <750000000>;
			clock-output-names = "vpu-clock";
		};

		clk_uart: clk-uart {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <9216000>;
			clock-output-names = "uart-clock";
		};

		clk_emmc2: clk-emmc2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
			clock-output-names = "emmc2-clock";
		};

		clk_sw_baud: clk-sw-baud {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <96000000>;
			clock-output-names = "sw-baud";
		};
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Source for L1 d/i cache-line-size, cache-sets, cache-size
		 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
		 * Source for L2 cache-line-size and cache-sets:
		 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
		 * and for cache-size:
		 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x000>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			i-cache-size = <0x10000>;

Annotation

Implementation Notes