arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts- Extension
.dts- Size
- 2057 bytes
- Lines
- 106
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
bcm2712-rpi-5-b-base.dtsirp1-common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* As a loose attempt to separate RP1 customizations from SoC peripherals
* definitioni, this file is intended to host the override nodes for the RP1
* peripherals, e.g. to declare the phy of the ethernet interface or custom
* pin setup.
* All other nodes that do not have anything to do with RP1 should be added
* to the included bcm2712-rpi-5-b-base.dtsi instead.
*/
/dts-v1/;
#include "bcm2712-rpi-5-b-base.dtsi"
/ {
aliases {
ethernet0 = &rp1_eth;
};
};
&pcie2 {
pci@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
bus-range = <0 1>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-common.dtsi"
};
};
};
&rp1_eth {
assigned-clocks = <&rp1_clocks RP1_CLK_ETH_TSU>,
<&rp1_clocks RP1_CLK_ETH>;
assigned-clock-rates = <50000000>,
<125000000>;
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&phy1>;
mdio {
reg = <0x1>;
reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
};
&rp1_gpio {
usb_vbus_default_state: usb-vbus-default-state {
function = "vbus1";
groups = "vbus1";
};
Annotation
- Immediate include surface: `bcm2712-rpi-5-b-base.dtsi`, `rp1-common.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.