arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi- Extension
.dtsi- Size
- 21713 bytes
- Lines
- 835
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/bcm-sr.hdt-bindings/interrupt-controller/arm-gic.hstingray-fs4.dtsistingray-pcie.dtsistingray-usb.dtsistingray-pinctrl.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <dt-bindings/clock/bcm-sr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,stingray";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x201>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
cpu@301 {
Annotation
- Immediate include surface: `dt-bindings/clock/bcm-sr.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `stingray-fs4.dtsi`, `stingray-pcie.dtsi`, `stingray-usb.dtsi`, `stingray-pinctrl.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.