arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi- Extension
.dtsi- Size
- 10372 bytes
- Lines
- 347
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/pinctrl/brcm,pinctrl-stingray.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
pinconf: pinctrl@140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
/* pinconf functions */
};
pinmux: pinmux@14029c {
compatible = "pinctrl-single";
reg = <0x0014029c 0x26c>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = <
&range 0 91 MODE_GPIO
&range 95 60 MODE_GPIO
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
/* pinctrl functions */
tsio_pins: gpio-14-pins {
pinctrl-single,pins = <
0x038 MODE_NITRO /* tsio_0 */
0x03c MODE_NITRO /* tsio_1 */
>;
};
nor_pins: pnor-adv-n-pins {
pinctrl-single,pins = <
0x0ac MODE_PNOR /* nand_ce1_n */
0x0b0 MODE_PNOR /* nand_ce0_n */
0x0b4 MODE_PNOR /* nand_we_n */
0x0b8 MODE_PNOR /* nand_wp_n */
0x0bc MODE_PNOR /* nand_re_n */
0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
0x0c4 MODE_PNOR /* nand_io0_0 */
0x0c8 MODE_PNOR /* nand_io1_0 */
0x0cc MODE_PNOR /* nand_io2_0 */
0x0d0 MODE_PNOR /* nand_io3_0 */
0x0d4 MODE_PNOR /* nand_io4_0 */
0x0d8 MODE_PNOR /* nand_io5_0 */
0x0dc MODE_PNOR /* nand_io6_0 */
0x0e0 MODE_PNOR /* nand_io7_0 */
0x0e4 MODE_PNOR /* nand_io8_0 */
0x0e8 MODE_PNOR /* nand_io9_0 */
0x0ec MODE_PNOR /* nand_io10_0 */
0x0f0 MODE_PNOR /* nand_io11_0 */
0x0f4 MODE_PNOR /* nand_io12_0 */
0x0f8 MODE_PNOR /* nand_io13_0 */
0x0fc MODE_PNOR /* nand_io14_0 */
0x100 MODE_PNOR /* nand_io15_0 */
0x104 MODE_PNOR /* nand_ale_0 */
0x108 MODE_PNOR /* nand_cle_0 */
0x040 MODE_PNOR /* pnor_adv_n */
0x044 MODE_PNOR /* pnor_baa_n */
0x048 MODE_PNOR /* pnor_bls_0_n */
0x04c MODE_PNOR /* pnor_bls_1_n */
0x050 MODE_PNOR /* pnor_cre */
0x054 MODE_PNOR /* pnor_cs_2_n */
0x058 MODE_PNOR /* pnor_cs_1_n */
0x05c MODE_PNOR /* pnor_cs_0_n */
0x060 MODE_PNOR /* pnor_we_n */
0x064 MODE_PNOR /* pnor_oe_n */
0x068 MODE_PNOR /* pnor_intr */
Annotation
- Immediate include surface: `dt-bindings/pinctrl/brcm,pinctrl-stingray.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.