arch/arm64/boot/dts/bst/bstc1200.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/bst/bstc1200.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/bst/bstc1200.dtsi
Extension
.dtsi
Size
2429 bytes
Lines
116
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "bst,c1200";
	#address-cells = <2>;
	#size-cells = <2>;

	clk_mmc: clock-4000000 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <4000000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_cache>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_cache>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x200>;
			enable-method = "psci";
			next-level-cache = <&l2_cache>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x300>;
			enable-method = "psci";
			next-level-cache = <&l2_cache>;
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc {
		compatible = "simple-bus";
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;

Annotation

Implementation Notes