arch/arm64/boot/dts/cix/sky1-pinfunc.h

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/cix/sky1-pinfunc.h

File Facts

System: Linux kernel
Corpus path: arch/arm64/boot/dts/cix/sky1-pinfunc.h
Extension: .h
Size: 24730 bytes
Lines: 402
Domain: Architecture Layer
Bucket: arch/arm64
Inferred role: Architecture Layer: implementation source
Status: source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __CIX_SKY1_H
#define __CIX_SKY1_H

/* s5 pads */
#define CIX_PAD_GPIO001_FUNC_GPIO001				   (0 << 8 | 0x0)
#define CIX_PAD_GPIO002_FUNC_GPIO002				   (1 << 8 | 0x0)
#define CIX_PAD_GPIO003_FUNC_GPIO003				   (2 << 8 | 0x0)
#define CIX_PAD_GPIO004_FUNC_GPIO004				   (3 << 8 | 0x0)
#define CIX_PAD_GPIO005_FUNC_GPIO005				   (4 << 8 | 0x0)
#define CIX_PAD_GPIO006_FUNC_GPIO006				   (5 << 8 | 0x0)
#define CIX_PAD_GPIO007_FUNC_GPIO007				   (6 << 8 | 0x0)
#define CIX_PAD_GPIO008_FUNC_GPIO008				   (7 << 8 | 0x0)
#define CIX_PAD_GPIO009_FUNC_GPIO009				   (8 << 8 | 0x0)
#define CIX_PAD_GPIO010_FUNC_GPIO010				   (9 << 8 | 0x0)
#define CIX_PAD_GPIO011_FUNC_GPIO011				   (10 << 8 | 0x0)
#define CIX_PAD_GPIO012_FUNC_GPIO012				   (11 << 8 | 0x0)
#define CIX_PAD_GPIO013_FUNC_GPIO013				   (12 << 8 | 0x0)
#define CIX_PAD_GPIO014_FUNC_GPIO014				   (13 << 8 | 0x0)
#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL			   (28 << 8 | 0x0)
#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL			   (28 << 8 | 0x1)
#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA			   (29 << 8 | 0x0)
#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA			   (29 << 8 | 0x1)
#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL			   (30 << 8 | 0x0)
#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL			   (30 << 8 | 0x1)
#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0			   (30 << 8 | 0x2)
#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA			   (31 << 8 | 0x0)
#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA			   (31 << 8 | 0x1)
#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1			   (31 << 8 | 0x2)
#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015				   (32 << 8 | 0x0)
#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK			   (32 << 8 | 0x1)
#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0			   (32 << 8 | 0x2)
#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016				   (33 << 8 | 0x0)
#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI			   (33 << 8 | 0x1)
#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1			   (33 << 8 | 0x2)
#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017				   (34 << 8 | 0x0)
#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO			   (34 << 8 | 0x1)
#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2			   (34 << 8 | 0x2)
#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3				   (35 << 8 | 0x0)
#define CIX_PAD_GPIO018_FUNC_GPIO018				   (35 << 8 | 0x1)
#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4				   (36 << 8 | 0x0)
#define CIX_PAD_GPIO019_FUNC_GPIO019				   (36 << 8 | 0x1)
#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5				   (37 << 8 | 0x0)
#define CIX_PAD_GPIO020_FUNC_GPIO020				   (37 << 8 | 0x1)
#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6				   (38 << 8 | 0x0)
#define CIX_PAD_GPIO021_FUNC_GPIO021				   (38 << 8 | 0x1)
#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7				   (39 << 8 | 0x0)
#define CIX_PAD_GPIO022_FUNC_GPIO022				   (39 << 8 | 0x1)
#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8				   (40 << 8 | 0x0)
#define CIX_PAD_GPIO023_FUNC_GPIO023				   (40 << 8 | 0x1)
#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L			   (40 << 8 | 0x2)
#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9				   (41 << 8 | 0x0)
#define CIX_PAD_GPIO024_FUNC_GPIO024				   (41 << 8 | 0x1)
#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L			   (41 << 8 | 0x2)
#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO			   (42 << 8 | 0x0)
#define CIX_PAD_SPI1_MISO_FUNC_GPIO025				   (42 << 8 | 0x1)
#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0				   (43 << 8 | 0x0)
#define CIX_PAD_SPI1_CS0_FUNC_GPIO026				   (43 << 8 | 0x1)
#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1				   (44 << 8 | 0x0)
#define CIX_PAD_SPI1_CS1_FUNC_GPIO027				   (44 << 8 | 0x1)
#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI			   (45 << 8 | 0x0)
#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028				   (45 << 8 | 0x1)
#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK				   (46 << 8 | 0x0)
#define CIX_PAD_SPI1_CLK_FUNC_GPIO029				   (46 << 8 | 0x1)
#define CIX_PAD_GPIO030_FUNC_GPIO030				   (47 << 8 | 0x0)
#define CIX_PAD_GPIO030_FUNC_USB_OC0_L				   (47 << 8 | 0x1)
#define CIX_PAD_GPIO031_FUNC_GPIO031				   (48 << 8 | 0x0)
#define CIX_PAD_GPIO031_FUNC_USB_OC1_L				   (48 << 8 | 0x1)
#define CIX_PAD_GPIO032_FUNC_GPIO032				   (49 << 8 | 0x0)
#define CIX_PAD_GPIO032_FUNC_USB_OC2_L				   (49 << 8 | 0x1)
#define CIX_PAD_GPIO033_FUNC_GPIO033				   (50 << 8 | 0x0)
#define CIX_PAD_GPIO033_FUNC_USB_OC3_L				   (50 << 8 | 0x1)
#define CIX_PAD_GPIO034_FUNC_GPIO034				   (51 << 8 | 0x0)
#define CIX_PAD_GPIO034_FUNC_USB_OC4_L				   (51 << 8 | 0x1)
#define CIX_PAD_GPIO035_FUNC_GPIO035				   (52 << 8 | 0x0)
#define CIX_PAD_GPIO035_FUNC_USB_OC5_L				   (52 << 8 | 0x1)
#define CIX_PAD_GPIO036_FUNC_GPIO036				   (53 << 8 | 0x0)
#define CIX_PAD_GPIO036_FUNC_USB_OC6_L				   (53 << 8 | 0x1)
#define CIX_PAD_GPIO037_FUNC_GPIO037				   (54 << 8 | 0x0)
#define CIX_PAD_GPIO037_FUNC_USB_OC7_L				   (54 << 8 | 0x1)
#define CIX_PAD_GPIO038_FUNC_GPIO038				   (55 << 8 | 0x0)
#define CIX_PAD_GPIO038_FUNC_USB_OC8_L				   (55 << 8 | 0x1)
#define CIX_PAD_GPIO039_FUNC_GPIO039				   (56 << 8 | 0x0)
#define CIX_PAD_GPIO039_FUNC_USB_OC9_L				   (56 << 8 | 0x1)
#define CIX_PAD_GPIO040_FUNC_GPIO040				   (57 << 8 | 0x0)
#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0			   (57 << 8 | 0x1)
#define CIX_PAD_GPIO041_FUNC_GPIO041				   (58 << 8 | 0x0)
#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4			   (58 << 8 | 0x1)
#define CIX_PAD_GPIO042_FUNC_GPIO042				   (59 << 8 | 0x0)
#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5			   (59 << 8 | 0x1)
#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK			   (60 << 8 | 0x0)

Annotation

Atlas domain: Architecture Layer / arch/arm64.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.