arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
Extension
.dtsi
Size
2231 bytes
Lines
121
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
 *
 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
 *             https://www.samsung.com
 * Copyright (c) 2025  Axis Communications AB.
 *             https://www.axis.com
 */

#include "artpec-pinctrl.h"

&pinctrl_fsys {
	gpe0: gpe0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpe1: gpe1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpe2: gpe2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf0: gpf0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf1: gpf1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf2: gpf2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf3: gpf3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf4: gpf4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gps0: gps0-gpio-bank {

Annotation

Implementation Notes