arch/arm64/boot/dts/exynos/exynos5433.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/exynos5433.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/exynos/exynos5433.dtsi
Extension
.dtsi
Size
54808 bytes
Lines
2005
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos5433 SoC device tree source
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *
 * Samsung's Exynos5433 SoC device nodes are listed in this file.
 * Exynos5433 based board files can include this file and provide
 * values for board specific bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
 * additional nodes can be added to this file.
 */

#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos5433";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	arm-a53-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	arm-a57-pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	xxti: clock {
		/* XXTI */
		compatible = "fixed-clock";
		clock-output-names = "oscclk";
		#clock-cells = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

Annotation

Implementation Notes