arch/arm64/boot/dts/exynos/exynos7885.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/exynos7885.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/exynos/exynos7885.dtsi- Extension
.dtsi- Size
- 11684 bytes
- Lines
- 471
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/exynos7885.hdt-bindings/interrupt-controller/arm-gic.hexynos7885-pinctrl.dtsiarm/samsung/exynos-syscon-restart.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung Exynos7885 SoC device tree source
*
* Copyright (c) 2021 Samsung Electronics Co., Ltd.
* Copyright (c) 2021 Dávid Virág
*/
#include <dt-bindings/clock/exynos7885.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "samsung,exynos7885";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_dispaud;
pinctrl2 = &pinctrl_fsys;
pinctrl3 = &pinctrl_top;
};
arm-a53-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>,
<&cpu4>,
<&cpu5>;
};
arm-a73-pmu {
compatible = "arm,cortex-a73-pmu";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu6>,
<&cpu7>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
Annotation
- Immediate include surface: `dt-bindings/clock/exynos7885.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `exynos7885-pinctrl.dtsi`, `arm/samsung/exynos-syscon-restart.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.