arch/arm64/boot/dts/exynos/exynos9810.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/exynos9810.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/exynos/exynos9810.dtsi
Extension
.dtsi
Size
6110 bytes
Lines
274
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * Samsung Exynos 9810 SoC device tree source
 *
 * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
 * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos9810";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_aud;
		pinctrl2 = &pinctrl_chub;
		pinctrl3 = &pinctrl_cmgp;
		pinctrl4 = &pinctrl_fsys0;
		pinctrl5 = &pinctrl_fsys1;
		pinctrl6 = &pinctrl_peric0;
		pinctrl7 = &pinctrl_peric1;
		pinctrl8 = &pinctrl_vts;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";

Annotation

Implementation Notes