arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi- Extension
.dtsi- Size
- 31505 bytes
- Lines
- 1190
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
exynos-pinctrl.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2021 Samsung Electronics Co., Ltd.
*
* Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
* device tree nodes in this file.
*/
#include "exynos-pinctrl.h"
&pinctrl_alive {
gpa0: gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
gpa1: gpa1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
};
dp0_hpd: dp0-hpd-pins {
samsung,pins = "gpa1-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
};
dp1_hpd: dp1-hpd-pins {
samsung,pins = "gpa1-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
};
gpq0: gpq0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
speedy0_bus: speedy0-bus-pins {
samsung,pins = "gpq0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
speedy1_bus: speedy1-bus-pins {
samsung,pins = "gpa0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
};
Annotation
- Immediate include surface: `exynos-pinctrl.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.