arch/arm64/boot/dts/exynos/google/gs101.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/google/gs101.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/exynos/google/gs101.dtsi
Extension
.dtsi
Size
53103 bytes
Lines
1865
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GS101 SoC
 *
 * Copyright 2019-2023 Google LLC
 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
 */

#include <dt-bindings/clock/google,gs101.h>
#include <dt-bindings/clock/google,gs101-acpm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>

/ {
	compatible = "google,gs101";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_gpio_alive;
		pinctrl1 = &pinctrl_far_alive;
		pinctrl2 = &pinctrl_gsacore;
		pinctrl3 = &pinctrl_gsactrl;
		pinctrl4 = &pinctrl_peric0;
		pinctrl5 = &pinctrl_peric1;
		pinctrl6 = &pinctrl_hsi1;
		pinctrl7 = &pinctrl_hsi2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu6>;
				};
				core1 {
					cpu = <&cpu7>;
				};
			};
		};

Annotation

Implementation Notes