arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi
Extension
.dtsi
Size
33110 bytes
Lines
1250
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GS101 SoC pin-mux and pin-config device tree source
 *
 * Copyright 2019-2023 Google LLC
 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
 */

#include "gs101-pinctrl.h"

&pinctrl_gpio_alive {
	gpa0: gpa0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	gpa1: gpa1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	gpa2: gpa2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	gpa3: gpa3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	gpa4: gpa4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

Annotation

Implementation Notes