arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi- Extension
.dtsi- Size
- 15597 bytes
- Lines
- 580
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/fsl,qoriq-clockgen.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/thermal/thermal.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for NXP Layerscape-1012A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019-2020 NXP
*
*/
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
crypto = &crypto;
rtc1 = &ftm_alarm0;
rtic-a = &rtic_a;
rtic-b = &rtic_b;
rtic-c = &rtic_c;
rtic-d = &rtic_d;
sec-mon = &sec_mon;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_PH20>;
};
};
idle-states {
/*
* PSCI node is not added default, U-boot will add missing
* parts if it determines to use PSCI.
*/
entry-method = "psci";
CPU_PH20: cpu-ph20 {
compatible = "arm,idle-state";
idle-state-name = "PH20";
arm,psci-suspend-param = <0x0>;
entry-latency-us = <1000>;
exit-latency-us = <1000>;
min-residency-us = <3000>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "sysclk";
};
coreclk: coreclk {
compatible = "fixed-clock";
#clock-cells = <0>;
Annotation
- Immediate include surface: `dt-bindings/clock/fsl,qoriq-clockgen.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/thermal/thermal.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.