arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts- Extension
.dts- Size
- 5676 bytes
- Lines
- 325
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
fsl-ls1043a.dtsifsl-ls1043-post.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018-2021 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
/dts-v1/;
#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
emi1-slot1 = &ls1043mdio_s1;
emi1-slot2 = &ls1043mdio_s2;
emi1-slot3 = &ls1043mdio_s3;
emi1-slot4 = &ls1043mdio_s4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
flash@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
Annotation
- Immediate include surface: `fsl-ls1043a.dtsi`, `fsl-ls1043-post.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.