arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
Extension
.dtsi
Size
29621 bytes
Lines
1063
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1088A family SoC.
 *
 * Copyright 2017-2020 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1088a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		rtc1 = &ftm_alarm0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* We have 2 clusters having 4 Cortex-A53 cores each */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			clocks = <&clockgen QORIQ_CLK_CMUX 1>;

Annotation

Implementation Notes