arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Extension
.dtsi
Size
4258 bytes
Lines
172
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
 *
 * Copyright 2014-2016 Freescale Semiconductor, Inc.
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"

/ {
	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};
};

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x100>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x101>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x200>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;

Annotation

Implementation Notes