arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi- Extension
.dtsi- Size
- 44639 bytes
- Lines
- 1654
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/pwm/pwm.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
ethernet0 = &fec1;
};
chosen {
stdout-path = &lpuart1;
};
/* Apalis BKL1 */
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bkl_on>;
brightness-levels = <0 45 63 88 119 158 203 255>;
default-brightness-level = <4>;
enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>;
status = "disabled";
};
gpio_fan: gpio-fan {
compatible = "gpio-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio8>;
gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
3000 1>;
};
/*
* Power management bus used to control LDO1OUT of the
* second PMIC PF8100. This is used for controlling voltage levels of
* typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
*
* IMX_SC_R_BOARD_R1 for 3.3V
* IMX_SC_R_BOARD_R2 for 1.8V
* IMX_SC_R_BOARD_R3 for 2.5V
* Note that for 2.5V operation the pad muxing needs to be changed,
* compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
*
* those power domains are mutually exclusive.
*/
reg_ext_rgmii: regulator-ext-rgmii {
compatible = "regulator-fixed";
power-domains = <&pd IMX_SC_R_BOARD_R1>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_EXT_RGMII (LDO1)";
regulator-state-mem {
regulator-off-in-suspend;
};
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3";
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
Annotation
- Immediate include surface: `dt-bindings/pwm/pwm.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.