arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
Extension
.dtsi
Size
12763 bytes
Lines
427
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019-2021 NXP
 * Zhou Guoniu <guoniu.zhou@nxp.com>
 */
img_ipg_clk: clock-img-ipg {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <200000000>;
	clock-output-names = "img_ipg_clk";
};

img_pxl_clk: clock-img-pxl {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <600000000>;
	clock-output-names = "img_pxl_clk";
};

img_subsys: bus@58000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x58000000 0x0 0x58000000 0x1000000>;

	isi: isi@58100000 {
		reg = <0x58100000 0x80000>;
		interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
			 <&pdma1_lpcg IMX_LPCG_CLK_0>,
			 <&pdma2_lpcg IMX_LPCG_CLK_0>,
			 <&pdma3_lpcg IMX_LPCG_CLK_0>,
			 <&pdma4_lpcg IMX_LPCG_CLK_0>,
			 <&pdma5_lpcg IMX_LPCG_CLK_0>,
			 <&pdma6_lpcg IMX_LPCG_CLK_0>,
			 <&pdma7_lpcg IMX_LPCG_CLK_0>;
		clock-names = "per0", "per1", "per2", "per3",
			      "per4", "per5", "per6", "per7";
		interrupt-parent = <&gic>;
		power-domains = <&pd IMX_SC_R_ISI_CH0>,
				<&pd IMX_SC_R_ISI_CH1>,
				<&pd IMX_SC_R_ISI_CH2>,
				<&pd IMX_SC_R_ISI_CH3>,
				<&pd IMX_SC_R_ISI_CH4>,
				<&pd IMX_SC_R_ISI_CH5>,
				<&pd IMX_SC_R_ISI_CH6>,
				<&pd IMX_SC_R_ISI_CH7>;
		status = "disabled";
	};

	irqsteer_csi0: irqsteer@58220000 {
		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
		reg = <0x58220000 0x1000>;
		#interrupt-cells = <1>;
		interrupt-controller;
		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&img_ipg_clk>;
		clock-names = "ipg";
		interrupt-parent = <&gic>;
		power-domains = <&pd IMX_SC_R_CSI_0>;
		fsl,channel = <0>;
		fsl,num-irqs = <32>;
	};

Annotation

Implementation Notes