arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
Extension
.dtsi
Size
11265 bytes
Lines
388
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

lsio_bus_clk: clock-lsio-bus {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	clock-output-names = "lsio_bus_clk";
};

lsio_subsys: bus@5d000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
		 <0x08000000 0x0 0x08000000 0x10000000>;

	lsio_pwm0: pwm@5d000000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d000000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
			 <&pwm0_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	lsio_pwm1: pwm@5d010000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d010000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
			 <&pwm1_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	lsio_pwm2: pwm@5d020000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d020000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
			 <&pwm2_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	lsio_pwm3: pwm@5d030000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d030000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
			 <&pwm3_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;

Annotation

Implementation Notes