arch/arm64/boot/dts/freescale/imx8dxl.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8dxl.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
Extension
.dtsi
Size
5938 bytes
Lines
271
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8dxl.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &eqos;
		gpio0 = &lsio_gpio0;
		gpio1 = &lsio_gpio1;
		gpio2 = &lsio_gpio2;
		gpio3 = &lsio_gpio3;
		gpio4 = &lsio_gpio4;
		gpio5 = &lsio_gpio5;
		gpio6 = &lsio_gpio6;
		gpio7 = &lsio_gpio7;
		mu1 = &lsio_mu1;
		spi0 = &lpspi0;
		spi1 = &lpspi1;
		spi2 = &lpspi2;
		spi3 = &lpspi3;
	};

	cpus: cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/* We have 1 clusters with 2 Cortex-A35 cores */
		A35_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			#cooling-cells = <2>;
			operating-points-v2 = <&a35_opp_table>;
		};

		A35_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			#cooling-cells = <2>;
			operating-points-v2 = <&a35_opp_table>;
		};

		A35_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

Annotation

Implementation Notes