arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi
Extension
.dtsi
Size
12567 bytes
Lines
445
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de>
 * 2025 Maud Spierings <maudspierings@gocontroll.com>
 */

#include "imx8mm.dtsi"

/ {
	model = "Ka-Ro Electronics TX8M-1610";
	compatible = "karo,tx8m-1610", "fsl,imx8mm";

	reg_3v3_etn: regulator-3v3-etn {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
		pinctrl-0 = <&pinctrl_reg_3v3_etn>;
		pinctrl-names = "default";
		regulator-boot-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "3v3-etn";
	};
};

&A53_0 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_1 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_2 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_3 {
	cpu-supply = <&reg_vdd_arm>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
	};
};

&fec1 {
	assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
			  <&clk IMX8MM_CLK_ENET_TIMER>,
			  <&clk IMX8MM_CLK_ENET_REF>,
			  <&clk IMX8MM_CLK_ENET_REF>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
				 <&clk IMX8MM_SYS_PLL2_100M>,
				 <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_50M>;
	assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>;
	clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
		 <&clk IMX8MM_CLK_ENET1_ROOT>,
		 <&clk IMX8MM_CLK_ENET_TIMER>,
		 <&clk IMX8MM_CLK_ENET_REF>;
	phy-handle = <&ethphy0>;
	phy-mode = "rmii";
	phy-reset-duration = <25>;

Annotation

Implementation Notes