arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
Extension
.dtsi
Size
11900 bytes
Lines
493
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

#include "imx8mn-overdrive.dtsi"

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
		spi0 = &flexspi;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
		clocks = <&osc_32k>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <80>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
&a53_opp_table {
	opp-1200000000 {
		opp-microvolt = <950000>;
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};

Annotation

Implementation Notes