arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso

File Facts

System

Linux kernel

Corpus path

arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso

Extension

.dtso

Size

628 bytes

Lines

43

Domain

Architecture Layer

Bucket

arch/arm64

Inferred role

Architecture Layer: arch/arm64

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• dt-bindings/gpio/gpio.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
 * D-82229 Seefeld, Germany.
 * Author: Alexander Stein
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

&backlight_lvds {
	status = "okay";
};

&dsi_lvds_bridge {
	status = "okay";
};

&expander0 {
	dsi-mux-oe-hog {
		gpio-hog;
		gpios = <10 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "DSI_MUX_OE#";
	};
};

&lcdif {
	status = "okay";
};

&mipi_dsi {
	samsung,burst-clock-frequency = <600000000>;
	status = "okay";
};

&panel {
	compatible = "tianma,tm070jvhg33";
	status = "okay";
};

Annotation

• Immediate include surface: `dt-bindings/gpio/gpio.h`.
• Atlas domain: Architecture Layer / arch/arm64.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.