arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi

File Facts

System

Linux kernel

Corpus path

arch/arm64/boot/dts/freescale/imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi

Extension

.dtsi

Size

615 bytes

Lines

38

Domain

Architecture Layer

Bucket

arch/arm64

Inferred role

Architecture Layer: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2022-2026 Marek Vasut
 */

&display_bl {
	pwms = <&pwm1 0 5000000 0>;
};

&i2c_dhpdk_panel {
	#address-cells = <1>;
	#size-cells = <0>;

	touch_lvds: touchscreen@41 {
		compatible = "ilitek,ili251x";
		reg = <0x41>;
		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
		touchscreen-size-x = <16384>;
		touchscreen-size-y = <9600>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
	};

	eeprom@50 {
		compatible = "atmel,24c04";
		reg = <0x50>;
		pagesize = <16>;
	};
};

&panel {
	compatible = "chefree,ch101olhlwh-002";
};

&pwm1 {
	status = "okay";
};

Annotation

• Atlas domain: Architecture Layer / arch/arm64.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.