arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso
Extension
.dtso
Size
981 bytes
Lines
45
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (C) 2025 PHYTEC Messtechnik GmbH
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx8mp-clock.h>

/dts-v1/;
/plugin/;

&backlight_lvds1 {
	brightness-levels = <0 8 16 32 64 128 255>;
	default-brightness-level = <8>;
	enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
	num-interpolated-steps = <2>;
	pwms = <&pwm3 0 50000 0>;
	status = "okay";
};

&lcdif2 {
	status = "okay";
};

&lvds_bridge {
	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
	/*
	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
	 * engine can reach accurate pixel clock of exactly 72.4 MHz.
	 */
	assigned-clock-rates = <0>, <506800000>;
	status = "okay";
};

&panel_lvds1 {
	compatible = "edt,etml1010g3dra";
	status = "okay";
};

&pwm3 {
	status = "okay";
};

Annotation

Implementation Notes