arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso
Extension
.dtso
Size
2755 bytes
Lines
109
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: arch/arm64
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (C) 2025 PHYTEC Messtechnik GmbH
 */

#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mp-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	wlbt_clock: clock-32768 {
		compatible = "fixed-clock";
		clock-accuracy = <20000>;
		clock-frequency = <32768>;
		clock-output-names = "WIFIBT_SLOW_CLK";
		#clock-cells = <0>;
	};

	usdhc1_pwrseq: pwr-seq {
		compatible = "mmc-pwrseq-simple";
		post-power-on-delay-ms = <250>;
		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
	};
};

&iomuxc {
	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS	0x140	/* RTS */
			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140	/* CTS */
			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140	/* RX */
			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140	/* TX */
		>;
	};

	pinctrl_bluetooth: bluetoothgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x106	/* BT_DEV_WAKE_EXP */
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x106	/* BT_REG_ON_EXP */
			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09	0x106	/* BT_HOST_WAKE_EXP */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190	/* SDIO_CLK */
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0	/* SDIO_CMD */
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0	/* SDIO_D0 */
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0	/* SDIO_D1 */
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0	/* SDIO_D2 */
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0	/* SDIO_D3 */
		>;
	};

	pinctrl_wifi: wifigrp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x106	/* WL_REG_ON_EXP */
		>;
	};
};

&uart3 {
	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	pinctrl-0 = <&pinctrl_uart3>;
	pinctrl-names = "default";

Annotation

Implementation Notes