arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
Extension
.dtsi
Size
13333 bytes
Lines
554
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
 * 2025 Maud Spierings <maudspierings@gocontroll.com>
 */

#include "imx8mp.dtsi"

/ {
	/* PHY regulator */
	regulator-3v3-etn {
		compatible = "regulator-fixed";
		gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		pinctrl-0 = <&pinctrl_reg_3v3_etn>;
		pinctrl-names = "default";
		regulator-always-on;
		regulator-boot-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "3v3-etn";
		vin-supply = <&reg_vdd_3v3>;
	};
};

&A53_0 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_1 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_2 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_3 {
	cpu-supply = <&reg_vdd_arm>;
};

&eqos {
	assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
			  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
			  <&clk IMX8MP_CLK_ENET_QOS>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
				 <&clk IMX8MP_SYS_PLL2_100M>,
				 <&clk IMX8MP_SYS_PLL2_50M>;
	assigned-clock-rates = <266000000>, <100000000>, <50000000>;
	nvmem-cells = <&eth_mac1>;
	phy-handle = <&ethphy0>;
	phy-mode = "rmii";
	pinctrl-0 = <&pinctrl_eqos>;
	pinctrl-1 = <&pinctrl_eqos_sleep>;
	pinctrl-names = "default", "sleep";
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&pinctrl_ethphy_rst_b>;
		pinctrl-names = "default";
		reset-delay-us = <25000>;
		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
			interrupt-parent = <&gpio4>;
			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;

Annotation

Implementation Notes