arch/arm64/boot/dts/freescale/imx8qm.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8qm.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8qm.dtsi
Extension
.dtsi
Size
14951 bytes
Lines
654
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		spi0 = &lpspi0;
		spi1 = &lpspi1;
		spi2 = &lpspi2;
		spi3 = &lpspi3;
		vpu-core0 = &vpu_core0;
		vpu-core1 = &vpu_core1;
		vpu-core2 = &vpu_core2;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};

			cluster1: cluster1 {
				core0 {
					cpu = <&A72_0>;
				};
				core1 {
					cpu = <&A72_1>;
				};
			};
		};

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;

Annotation

Implementation Notes