arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
Extension
.dtsi
Size
6151 bytes
Lines
212
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/delete-node/ &adma_pwm;
/delete-node/ &adma_pwm_lpcg;

&dma_subsys {
	uart4_lpcg: clock-controller@5a4a0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a4a0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart4_lpcg_baud_clk",
				     "uart4_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_4>;
	};

	i2c4: i2c@5a840000 {
		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
		reg = <0x5a840000 0x4000>;
		interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&i2c4_lpcg 0>,
			 <&i2c4_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_4>;
		status = "disabled";
	};

	i2c4_lpcg: clock-controller@5ac40000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac40000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c4_lpcg_clk",
				     "i2c4_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_4>;
	};

	can1_lpcg: clock-controller@5ace0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ace0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>, <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
		clock-output-names = "can1_lpcg_pe_clk",
				     "can1_lpcg_ipg_clk",
				     "can1_lpcg_chi_clk";
		power-domains = <&pd IMX_SC_R_CAN_1>;
	};

	can2_lpcg: clock-controller@5acf0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5acf0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>, <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
		clock-output-names = "can2_lpcg_pe_clk",
				     "can2_lpcg_ipg_clk",

Annotation

Implementation Notes