arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
Extension
.dtsi
Size
7792 bytes
Lines
253
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2024 NXP
 *	Richard Zhu <hongxing.zhu@nxp.com>
 */

&hsio_subsys {
	compatible = "simple-bus";
	ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
		 <0x40000000 0x0 0x60000000 0x10000000>,
		 <0x80000000 0x0 0x70000000 0x10000000>;
	#address-cells = <1>;
	#size-cells = <1>;

	pcie0: pciea: pcie@5f000000 {
		compatible = "fsl,imx8q-pcie";
		reg = <0x5f000000 0x10000>,
		      <0x4ff00000 0x80000>;
		reg-names = "dbi", "config";
		ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
			 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
		#interrupt-cells = <1>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi", "dma";
		#address-cells = <3>;
		#size-cells = <2>;
		clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
			 <&pciea_lpcg IMX_LPCG_CLK_4>,
			 <&pciea_lpcg IMX_LPCG_CLK_5>;
		clock-names = "dbi", "mstr", "slv";
		bus-range = <0x00 0xff>;
		device_type = "pci";
		interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-map-mask = <0 0 0 0x7>;
		num-lanes = <1>;
		num-viewport = <4>;
		power-domains = <&pd IMX_SC_R_PCIE_A>;
		fsl,max-link-speed = <3>;
		status = "disabled";

		pciea_port0: pcie@0 {
			compatible = "pciclass,0604";
			device_type = "pci";
			reg = <0x0 0x0 0x0 0x0 0x0>;
			bus-range = <0x01 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
		};
	};

	pcie0_ep: pciea_ep: pcie-ep@5f000000 {
		compatible = "fsl,imx8q-pcie-ep";
		reg = <0x5f000000 0x00010000>,
		      <0x40000000 0x10000000>;
		reg-names = "dbi", "addr_space";
		num-lanes = <1>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "dma";
		clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
			 <&pciea_lpcg IMX_LPCG_CLK_4>,
			 <&pciea_lpcg IMX_LPCG_CLK_5>;
		clock-names = "dbi", "mstr", "slv";
		power-domains = <&pd IMX_SC_R_PCIE_A>;
		fsl,max-link-speed = <3>;

Annotation

Implementation Notes