arch/arm64/boot/dts/freescale/imx8ulp.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/imx8ulp.dtsi- Extension
.dtsi- Size
- 28827 bytes
- Lines
- 947
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/imx8ulp-clock.hdt-bindings/gpio/gpio.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/power/imx8ulp-power.hdt-bindings/thermal/thermal.himx8ulp-pinfunc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8ulp-pinfunc.h"
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec;
gpio0 = &gpiod;
gpio1 = &gpioe;
gpio2 = &gpiof;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
spi0 = &lpspi4;
spi1 = &lpspi5;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
A35_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
cpu-idle-states = <&cpu_sleep>;
};
A35_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
cpu-idle-states = <&cpu_sleep>;
};
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
entry-method = "psci";
cpu_sleep: cpu-sleep {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0>;
local-timer-stop;
entry-latency-us = <1000>;
Annotation
- Immediate include surface: `dt-bindings/clock/imx8ulp-clock.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/power/imx8ulp-power.h`, `dt-bindings/thermal/thermal.h`, `imx8ulp-pinfunc.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.