arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts- Extension
.dts- Size
- 24333 bytes
- Lines
- 1038
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
dt-bindings/leds/common.hdt-bindings/phy/phy-imx8-pcie.hdt-bindings/pwm/pwm.hdt-bindings/usb/pd.himx95.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */
#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */
#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */
#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */
#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */
/ {
compatible = "fsl,imx95-15x15-frdm", "fsl,imx95";
model = "NXP i.MX95 15X15 FRDM board";
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &lpuart1;
serial4 = &lpuart5;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
stdout-path = &lpuart1;
};
dmic: dmic {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
num-channels = <2>;
};
flexcan2_phy: can-phy {
compatible = "nxp,tja1051";
#phy-cells = <0>;
max-bitrate = <5000000>;
/*
* Shared SILENT GPIO: CAN PHYs enter silent mode
* together (hardware design).
*/
silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>;
};
flexcan5_phy: can-phy {
Annotation
- Immediate include surface: `dt-bindings/leds/common.h`, `dt-bindings/phy/phy-imx8-pcie.h`, `dt-bindings/pwm/pwm.h`, `dt-bindings/usb/pd.h`, `imx95.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.