arch/arm64/boot/dts/freescale/imx95.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/imx95.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/freescale/imx95.dtsi- Extension
.dtsi- Size
- 67873 bytes
- Lines
- 2312
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/clock/nxp,imx95-clock.hdt-bindings/dma/fsl-edma.hdt-bindings/gpio/gpio.hdt-bindings/input/input.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/thermal/thermal.himx95-clock.himx95-pinfunc.himx95-power.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Copyright 2024 NXP
*/
#include <dt-bindings/clock/nxp,imx95-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx95-clock.h"
#include "imx95-pinfunc.h"
#include "imx95-power.h"
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <10000>;
exit-latency-us = <7000>;
min-residency-us = <27000>;
wakeup-latency-us = <15000>;
};
};
A55_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l0>;
};
A55_1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
Annotation
- Immediate include surface: `dt-bindings/clock/nxp,imx95-clock.h`, `dt-bindings/dma/fsl-edma.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/input/input.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/thermal/thermal.h`, `imx95-clock.h`, `imx95-pinfunc.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.