arch/arm64/boot/dts/freescale/s32g2.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/s32g2.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/s32g2.dtsi
Extension
.dtsi
Size
19753 bytes
Lines
863
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * NXP S32G2 SoC family
 *
 * Copyright (c) 2021 SUSE LLC
 * Copyright 2017-2021, 2024-2026 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory  {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scmi_buf: shm@d0000000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0xd0000000 0x0 0x80>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

Annotation

Implementation Notes