arch/arm64/boot/dts/freescale/s32g3.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/s32g3.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/s32g3.dtsi
Extension
.dtsi
Size
24371 bytes
Lines
1021
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright 2021-2026 NXP
 *
 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
 *          Ciprian Costea <ciprianmarian.costea@nxp.com>
 *          Andra-Teodora Ilie <andra.ilie@nxp.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g3";
	interrupt-parent = <&gic>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&dfs 0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";

Annotation

Implementation Notes