arch/arm64/boot/dts/freescale/s32n79.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/s32n79.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/s32n79.dtsi
Extension
.dtsi
Size
7597 bytes
Lines
363
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * NXP S32N79 SoC
 *
 * Copyright 2026 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cis-bus {
		compatible = "simple-bus";
		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
		#address-cells = <1>;
		#size-cells = <1>;

		gic: interrupt-controller@4f200000 {
			compatible = "arm,gic-v3";
			reg = <0x4f200000 0x10000>, /* GIC Dist */
			      <0x4f260000 0x100000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			/* GICR (RD_base + SGI_base) */
			ranges;

			its: msi-controller@4f240000 {
				compatible = "arm,gic-v3-its";
				reg = <0x4f240000 0x20000>;
				#msi-cells = <1>;
				msi-controller;
			};
		};

		smmu: iommu@4fc00000 {
			compatible = "arm,smmu-v3";
			reg = <0x4fc00000 0x200000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
			#iommu-cells = <1>;
			dma-coherent;
			status = "disabled";
		};
	};

	coss-bus {
		compatible = "simple-bus";
		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
			 <0x4e000000 0x0 0x4e000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@4a030000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x4a030000 0x1000>;
			interrupt-parent = <&irqsteer_coss>;
			interrupts = <264>;
			clocks = <&clks 0x9a>, <&clks 0x9a>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";

Annotation

Implementation Notes