arch/arm64/boot/dts/freescale/s32v234.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/freescale/s32v234.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/freescale/s32v234.dtsi
Extension
.dtsi
Size
3265 bytes
Lines
144
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016-2018 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	compatible = "fsl,s32v234";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cluster0_l2_cache: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		cluster1_l2_cache: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;

Annotation

Implementation Notes