arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
Extension
.dtsi
Size
17527 bytes
Lines
662
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * DTS File for HiSilicon Hi3798cv200 SoC.
 *
 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
 */

#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>

/ {
	compatible = "hisilicon,hi3798cv200";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
			d-cache-size = <0x8000>; /* 32 KiB */
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			i-cache-size = <0x8000>; /* 32 KiB */
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
			d-cache-size = <0x8000>; /* 32 KiB */
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			i-cache-size = <0x8000>; /* 32 KiB */
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
			d-cache-size = <0x8000>; /* 32 KiB */
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			i-cache-size = <0x8000>; /* 32 KiB */
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&L2>;
		};

Annotation

Implementation Notes