arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi- Extension
.dtsi- Size
- 21712 bytes
- Lines
- 1061
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/pinctrl/hisi.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* pinctrl dts fils for Hislicon HiKey960 development board
*
*/
#include <dt-bindings/pinctrl/hisi.h>
/ {
soc {
/* [IOMG_000, IOMG_123] */
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
pmx0: pinmux@e896c000 {
compatible = "pinctrl-single";
reg = <0x0 0xe896c000 0x0 0x1f0>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <
&range 0 7 0
&range 8 116 0>;
pmu_pmx_func: pmu-pins {
pinctrl-single,pins = <
0x008 MUX_M1 /* PMU1_SSI */
0x00c MUX_M1 /* PMU2_SSI */
0x010 MUX_M1 /* PMU_CLKOUT */
0x100 MUX_M1 /* PMU_HKADC_SSI */
>;
};
csi0_pwd_n_pmx_func: csi0-pwd-n-pins {
pinctrl-single,pins = <
0x044 MUX_M0 /* CSI0_PWD_N */
>;
};
csi1_pwd_n_pmx_func: csi1-pwd-n-pins {
pinctrl-single,pins = <
0x04c MUX_M0 /* CSI1_PWD_N */
>;
};
isp0_pmx_func: isp0-pins {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
0x064 MUX_M1 /* ISP_SCL0 */
0x068 MUX_M1 /* ISP_SDA0 */
>;
};
isp1_pmx_func: isp1-pins {
pinctrl-single,pins = <
0x05c MUX_M1 /* ISP_CLK1 */
0x06c MUX_M1 /* ISP_SCL1 */
0x070 MUX_M1 /* ISP_SDA1 */
>;
};
pwr_key_pmx_func: pwr-key-pins {
pinctrl-single,pins = <
0x080 MUX_M0 /* GPIO_034 */
>;
};
Annotation
- Immediate include surface: `dt-bindings/pinctrl/hisi.h`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.