arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
Extension
.dtsi
Size
23046 bytes
Lines
952
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2023, Intel Corporation
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/intel,agilex5-clkmgr.h>

/ {
	compatible = "intel,socfpga-agilex5";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x80000000 0x0 0x2000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&L2>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&L2>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a76";
			reg = <0x200>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&L2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a76";
			reg = <0x300>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			next-level-cache = <&L3>;

Annotation

Implementation Notes