arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
Extension
.dts
Size
1823 bytes
Lines
115
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2023, Intel Corporation
 */
#include "socfpga_agilex5.dtsi"

/ {
	model = "SoCFPGA Agilex5 SoCDK";
	compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";

	aliases {
		serial0 = &uart0;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
		i3c0 = &i3c0;
		i3c1 = &i3c1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "hps_led0";
			gpios = <&porta 11 GPIO_ACTIVE_HIGH>;
		};

	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0x0 0x80000000 0x0 0x0>;
	};
};

&gpio0 {
	status = "okay";
};

&gmac2 {
	status = "okay";
	phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
	phy-handle = <&emac2_phy0>;
	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		emac2_phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&gpio1 {
	status = "okay";
};

&osc1 {
	clock-frequency = <25000000>;
};

&qspi {

Annotation

Implementation Notes