arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts- Extension
.dts- Size
- 2292 bytes
- Lines
- 129
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
socfpga_agilex.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
/ {
model = "eASIC N5X SoCDK";
compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0x80000000 0 0>;
};
soc@0 {
sdram_edac: memory-controller@f87f8000 {
compatible = "snps,ddrc-3.80a";
reg = <0xf87f8000 0x400>;
interrupts = <0 175 4>;
};
};
};
&clkmgr {
compatible = "intel,easic-n5x-clkmgr";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
Annotation
- Immediate include surface: `socfpga_agilex.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.