arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

File Facts

System
Linux kernel
Corpus path
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
Extension
.dtsi
Size
8685 bytes
Lines
369
Domain
Architecture Layer
Bucket
arch/arm64
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree For AC5.
 *
 * Copyright (C) 2021 Marvell
 * Copyright (C) 2022 Allied Telesis Labs
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell AC5 SoC";
	compatible = "marvell,ac5";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {

Annotation

Implementation Notes