arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts- Extension
.dts- Size
- 1706 bytes
- Lines
- 45
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
cn9131-db-comexpress.dtsiac5x-rd-carrier.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Marvell International Ltd.
*
* Device tree for the AC5X RD Type 7 Com Express carrier board,
* Utilizing the CN913x COM Express CPU module board.
* This specific carrier board in this mode of operation (external)
* only maintains a PCIe link with the CPU module,
* which does not require any special DTS definitions.
*
* AC5X RD works here in external mode (switch selectable at the back of the
* board), and connect via an external cable a kit
* which would allow it to use an external CN9131 CPU COM Express module,
* mounted on top of an interposer kit.
*
* So in this case, once the switch is set to external mode as explained above,
* the AC5X RD becomes part of the carrier solution.
*
* When the board boots in the external CPU mode, the internal CPU is disabled,
* and only the switch portion of the SOC acts as a PCIe end-point, Hence there
* is no need to describe this internal (disabled CPU) in the device tree.
*
* There is no CPU booting in this mode on the carrier, only on the
* CN9131 COM Express CPU module.
* What runs the Linux is the CN9131 on the COM Express CPU module,
* And it accesses the switch end-point on the AC5X RD portion of the carrier
* via PCIe.
*/
#include "cn9131-db-comexpress.dtsi"
#include "ac5x-rd-carrier.dtsi"
/ {
model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",
"marvell,cn9131-cpu-module", "marvell,cn9131",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x2 0x00000000>;
};
};
Annotation
- Immediate include surface: `cn9131-db-comexpress.dtsi`, `ac5x-rd-carrier.dtsi`.
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.