arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
Source file repositories/reference/linux-study-clean/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi- Extension
.dtsi- Size
- 1433 bytes
- Lines
- 35
- Domain
- Architecture Layer
- Bucket
- arch/arm64
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Marvell International Ltd.
*
* Device tree for the AC5X RD Type 7 Com Express carrier board,
* This specific board in external mode (see below) only maintains
* a PCIe link with the COM Express CPU module, which does not
* require any special DTS definitions.
*
* AC5X RD can either work as you would expect, as a complete standalone
* box using the internal CPU, or you can move the switch on the back of
* the box to "external" mode, and connect via an external cable a kit
* which would allow it to use an external CPU COM Express module,
* mounted on top of an interposer kit.
*
* So in this case, once the switch is set to external mode as explained above,
* the AC5X RD becomes part of the carrier solution.
* This is a development/reference solution, not a full commercial solution,
* hence it was designed with the flexibility to be configured in different
* modes of operation.
*
* When the board boots in the external CPU mode, the internal CPU is disabled,
* and only the switch portion of the SOC acts as a PCIe end-point, Hence there
* is no need to describe this internal (disabled CPU) in the device tree.
*
* There is no CPU booting in this mode on the carrier,
* only on the COM Express CPU module.
*/
/ {
model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
compatible = "marvell,rd-ac5x-carrier";
};
Annotation
- Atlas domain: Architecture Layer / arch/arm64.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.